Present computer systems rely on communication bus architectures to communicate information between system components, such as between the central processor unit (CPU), memory, and input/output (I/O) devices. Many industry standards have developed defining the construction and operation of the bus and the communication signals on the bus, such as the Peripheral Components Interconnect (PCI), promoting interoperability among different computer system components offered by different hardware vendors that would otherwise not be interoperable. These standard busses include a shared physical connection interconnecting each of the system components, where each of the system components is addressable by some means.
The advantages of using a shared bus, however, result in some amount of unavoidable, operational inefficiencies. For example, if each system component is allowed unrestricted access to the bus, there will be instances where two or more system components attempt to simultaneously access the bus. Simultaneous access of the bus by two or more system components attempting to transmit during the same time period would result the respective transmit signals of each system component overlapping and becoming garbled. Such a scenario could result in the propagation of errors, or more likely, that each system component would need to re-send the same message again. To avoid multiple bus components attempting to transmit on the bus during the same time period, bus-design standards include some means of arbitration ensuring that only one system component transmits across the bus during a given time period.
In an arbitrated bus system, a bus arbiter receives requests for bus access from multiple system components and grants access to the bus to only one system component during one time period. Although this arbitration capability improves efficiency by eliminating the need to re-send data resulting from interfering transmissions by multiple system components, any benefit comes at the cost of additional overhead resulting from the arbitration procedure. Typically, an arbiter grants access for a predetermined time period or bandwidth window to whichever bus requester first requests use of the bus. If multiple bus requesters have requests for use of the bus pending, then the arbiter typically employs a rotational priority scheme to share the bus among the bus requesters. In a rotational priority scheme, the use of the bus is given for one bandwidth window to each bus requester in sequential order. Thus, the rotational priority scheme gives each bus requester the same amount of bus time as every other bus requester connected to the bus.
One problem with the prior art arbitration schemes is that each bus requester can only generate a single bus request at a time. That is because each bus requester must keep its first bus request active until the arbiter selects the bus request. Upon selecting the first bus request of a selected bus requester, the arbiter captures the selected bus request in a latch and then transmits the bus request on the computer bus when the computer bus becomes available. In addition, the arbiter transmits to the selected bus requester an acknowledgment indicating that selected bus request was captured. In response to receiving the acknowledgment from the arbiter, the selected bus requester can generate and transmit a second bus request to the arbiter. Each of the other bus requesters similarly must wait until its first bus request is selected before generating a second bus request. As such, high bandwidth bus requesters are prevented from generating bus requests at their optimum speed.
The present invention solves this problem.